Electrical products are becoming lighter, thinner, shorter, and smaller, and DRAMs are being scaled down to match the trends of high integration and high density. A DRAM including many memory cells is one of the most popular volatile memory devices utilized today. Each memory cell includes a transistor and at least a capacitor, wherein the transistor and the capacitor form a series connection with each other. The memory cells are arranged into memory arrays. The memory cells are addressed via a word line and a digit line (or bit line), one of which addresses a column of memory cells while the other addresses a row of memory cells. By using the word line and the digit line, a DRAM cell can be read and programmed.
Recently, there has been increasing research on the buried word line cell array transistor, in which a word line is buried in a semiconductor substrate below the top surface of the substrate using a metal as a gate conductor. However, as the reduction of the device size also reduces the distance between the word lines and the bit lines, word line disturbance is observed in adjacent word lines. When the word line disturbance becomes serious, performance of the DRAM cell is degraded.
This Discussion of the Background section is for background information only. The statements in this Discussion of the Background are not an admission that the subject matter disclosed in this section constitutes a prior art to the present disclosure, and no part of this section may be used as an admission that any part of this application, including this Discussion of the Background section, constitutes prior art to the present disclosure.